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HT83XXX Q-VoiceTM
Technical Document
* Tools Information * FAQs * Application Note
Features
* Operating voltage: 2.4V~5.2V * Up to 1ms (0.5ms) instruction cycle with 4MHz (8MHz) * Two 8-bit programmable timer counter with 8-stage
prescaler and one time base counter
* Watchdog Timer * 4-level subroutine nesting * HALT function and wake-up feature reduce power
system clock
* System clock: 4MHz~8MHz (2.4V) * Crystal or RC oscillator for system clock * 12 I/O pins * 2K15 program ROM * 808 RAM
consumption
* PWM circuit direct drive speaker or output by
transistor
* 28-pin SOP package
Applications
* Intelligent educational leisure products * Alert and warning systems * Sound effect generators
General Description
The HT83XXX is 8-bit high performance microcontroller with voice synthesizer and tone generator. The HT83XXX is designed for applications on multiple I/Os with sound effects, such as voice and melody. It can provide various sampling rates and beats, tone levels, tempos for speech synthesizer and melody generator. The HT83XXX is excellent for versatile voice and sound effect product applications. The efficient MCU instructions allow users to program the powerful custom applications. The system frequency of HT83XXX can be up to 8MHz under 2.4V and include a HALT function to reduce power consumption.
Selection Table
Body Voice ROM Size Voice Length HT83004 64K-bit 3 sec HT83007 128K-bit 6 sec HT83010 192K-bit 9 sec HT83020 384K-bit 18 sec HT83038 768K-bit 36 sec HT83050 1024K-bit 48 sec HT83074 1536K-bit 72 sec
Rev. 1.20
1
May 17, 2007
HT83XXX
Block Diagram
STACK0 STACK1 P ro g ra m ROM P ro g ra m C o u n te r STACK2 STACK3 IN T C In te rru p t C ir c u it
TM R0 TM R0C
8 - s ta g e P r e s c a le r
SYS C LK
8 - b it
TM R1 In s tr u c tio n R e g is te r MP0 M U X TM R1C
8 - s ta g e P r e s c a le r
SYS C LK
D a ta M e m o ry
8 - b it
T im e B a s e
S Y S C L K /1 0 2 4
S Y S C L K /4
In s tr u c tio n D ecoder ALU T im in g G e n e r a tio n
MUX
PAC PA
STATUS
PORT A
PA0~PA7
S h ifte r
PBC PB
W DTS
PORT B
PB0~PB3
OSC2
OS RE VD VS
C1 S D S
ACC
M 256 U
W DTRC OSC X S Y S C L K /4
W D T P r e s c a le r
SYS C LK PW M PW M1 PW M2
Pin Assignment
NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NC NC PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 NC NC NC PW M2 PW M1 VDDA VDD VSS VSSA OSC1 OSC2 RES NC PB3
H T 8 3 0 0 4 /H T 8 3 0 0 7 /H T 8 3 0 1 0 /H T 8 3 0 2 0 /H T 8 3 0 3 8 /H T 8 3 0 5 0 /H T 8 3 0 7 4 2 8 S O P -A
Rev. 1.20
2
May 17, 2007
HT83XXX
Pad Assignment
HT83004/HT83007/HT83010
PA0 1 2 3 4 5 6 7 8 9 PA1 PA2 PA3 PA4 PA5 PA6 PA7
21 20 19 18 17 16 15 10 11 PB2 12 PB3 13 RES 14
PW M2 PW M1 VDDA VDD VSSA VSS OSC1 OSC2
(0 ,0 )
* The IC substrate should be connected to VSS in the PCB layout artwork. HT83020/HT83038
PB1 PB0
Chip size: 22801475 (mm)2
PA0 PA1 1 2 3 4 5 6 7 8 9 PA2 PA3 PA4 PA5 PA6 PA7
21 (0 ,0 ) 20 19 18 17 16 10 11 12 13 RES 15 14
PW M2 PW M1 VDDA VDD VSSA VSS OSC1 OSC2
* The IC substrate should be connected to
PB PB PB PB 0 1 2 3
Chip size: 21801720 (mm)2 in the PCB layout artwork.
Rev. 1.20
3
May 17, 2007
HT83XXX
HT83050/HT83074
PA0 PA1 2 3 4 5 6 7 8 9 PA2 PA3 PA4 PA5 PA6 PA7
1
(0 ,0 ) 21 20 19 18 17 16 15 10 11 12 13 PB3 PB2 RES 14 PW M2 PW M1 VDDA VDD VSSA VSS OSC1 OSC2
* The IC substrate should be connected to
PB1 PB0
Chip size: 21802075 (mm)2 in the PCB layout artwork.
Pad Coordinates
HT83004/HT83007/HT83010 Pad No. 1 2 3 4 5 6 7 8 9 10 11 HT83020/HT83038 Pad No. 1 2 3 4 5 6 7 8 9 10 11 X -940.400 -940.400 -940.400 -940.400 -940.400 -940.400 -940.400 -940.400 -947.200 -852.200 -749.200 Y 184.650 89.650 -13.350 -108.350 -211.350 -306.350 -409.350 -504.350 -710.400 -710.400 -710.400 Pad No. 12 13 14 15 16 17 18 19 20 21 X -654.200 -551.200 940.400 940.400 940.600 940.600 896.250 904.900 904.900 904.900 Y -710.400 -710.400 -693.700 -598.700 -491.000 -395.500 -285.750 -185.750 -66.200 144.300 X -940.400 -940.400 -940.400 -940.400 -940.400 -940.400 -940.400 -940.400 -947.200 -852.200 -749.200 Y 307.150 212.150 109.150 14.150 -88.850 -183.850 -286.850 -381.850 -587.900 -587.900 -587.900 Pad No. 12 13 14 15 16 17 18 19 20 21 X -654.200 -551.200 940.400 940.400 940.600 940.600 896.250 904.900 904.900 904.900 Y -587.900 -587.900 -571.200 -476.200 -368.500 -273.000 -165.350 -63.250 56.300 266.800
Rev. 1.20
4
May 17, 2007
HT83XXX
HT83050/HT83074 Pad No. 1 2 3 4 5 6 7 8 9 10 11 X -940.400 -940.400 -940.400 -940.400 -940.400 -940.400 -940.400 -940.400 -947.200 -852.200 -749.200 Y 7.150 -87.850 -190.850 -285.850 -388.850 -483.850 -586.850 -681.850 -887.900 -887.900 -887.900 Pad No. 12 13 14 15 16 17 18 19 20 21 X -654.200 -551.200 940.400 940.400 940.600 940.600 896.250 904.900 904.900 904.900 Y -887.900 -887.900 -871.200 -776.200 -668.500 -573.000 -463.250 -363.250 -243.700 -33.200
Pad Description
Pad Name PA0~PA7 I/O I/O Mask Option Wake-up, Pull-high or None Pull-high or None 3/4 3/4 3/4 3/4 3/4 RC or Crystal Description Bidirectional 8-bit I/O port. Each bit can be configured as a wake-up input by mask option. Software instructions determine the output or Schmitt trigger input with or without pull-high resistor (mask option). Bidirectional 4-bit I/O port. Software instructions determine the CMOS output or Schmitt trigger input (pull-high resistor depending on mask option). Negative power supply, ground Positive power supply PWM negative power supply, ground PWM positive power supply, ground Schmitt trigger reset input, active low OSC1 and OSC2 are connected to an RC network or crystal (by mask option) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. The system clock may came form the crystal, the two pins cannot be floating. PWM output for driving a external transistor or speaker
PB0~PB3
I/O 3/4 3/4 3/4 3/4
RES OSC1, OSC2 PWM1, PWM2
I
3/4
O
3/4
Absolute Maximum Ratings
Supply Voltage ..........................VSS+2.4V to VSS+5.5V Input Voltage .............................VSS-0.3V to VDD+0.3V Storage Temperature ...........................-50C to 125C Operating Temperature ..........................-20C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.20
5
May 17, 2007
HT83XXX
D.C. Characteristics
Symbol VDD ISTB1 Parameter Operating Voltage Standby Current (Watchdog Off) 5V ISTB2 3V Standby Current (Watchdog On) 5V IDD 3V Operating Current 5V IOL1 3V I/O Port Sink Current 5V IOH1 3V I/O Port Source Current 5V IOL2 3V PWM1/PWM2 Sink Current 5V IOH2 3V PWM1/PWM2 Source Current 5V VIL1 3V Input Low Voltage for I/O Ports 5V VIH1 3V Input High Voltage for I/O Ports 5V VIL2 3V Reset Low Voltage (RES) 5V VIH2 3V Reset High Voltage (RES) 5V fSYS System Frequency 3V 3V Pull-high Resistance 5V 3/4 VOH=0.9VDD VOL=0.1VDD VOH=0.9VDD VOL=0.1VDD No load, fSYS=4MHz No load, system HALT Test Conditions VDD Conditions Min. 2.4 3/4 3/4 3/4 3/4 3/4 3/4 7 15 -3.5 -8 50 100 -14.5 -26 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 20 10 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 1 2 2 3.2 1.5 2.5 2.1 3.5 4.0 8.0 60 30 Max. 5.2 1 2 2 4 2 5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 100 50 Unit V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V V V V V V V MHz MHz kW kW
3/4 fSYS=4MHz/8MHz 3V No load, system HALT
3/4
3/4
3/4 RTYPICAL=275kW RTYPICAL=144kW
RPH
3/4
Rev. 1.20
6
May 17, 2007
HT83XXX
A.C. Characteristics
Symbol fSYS1 fSYS2 fTIMER Parameter System Clock (RC OSC) System Clock (Crystal OSC) Timer Input Frequency Test Conditions VDD 3/4 2.4V~5.2V 3/4 2.4V~5.2V 3/4 2.4V~5.2V 3V 5V tWDT1 tWDT2 tRES tSST tINT tDRT tDRR Watchdog Time-out Period (WDT OSC) Watchdog Time-out Period (System Clock) 3V Without WDT prescaler 5V 3/4 Without WDT prescaler 3/4 8 3/4 1 3/4 1 5 30 17 1024 3/4 1024 3/4 3/4 3/4 33 3/4 3/4 3/4 3/4 3/4 3/4 ms tSYS ms tSYS ms ms ms 3/4 Conditions Min. Typ. Max. Unit 4 4 0 50 37 12 3/4 3/4 3/4 100 74 23 8 8 8 200 148 46 MHz MHz MHz ms ms ms
tWDTOSC Watchdog Oscillator Period
External Reset Low Pulse Width 3/4 System Start-up Timer Period Interrupt Pulse Width Data ROM Access Timer Data ROM enable Read
3/4 Power-up or Wake-up from HALT 3/4 3/4 3/4 3/4
3/4 Read after data ROM enable
Characteristics Curves
R vs. F Characteristics Curve
H T83XXX 10 R v s . F C h a rt
8 4 .5 V F re q u e n c y (M H z ) 6 3V
4
2
0 144 R 188 (k W ) 275 560
Rev. 1.20
7
May 17, 2007
HT83XXX
V vs. F Characteristics Curve
H T83XXX 10
V v s . F C h a r t (F o r 3 .0 V )
8 F re q u e n c y (4 M H z ) 8 M H z /1 4 4 k W 6
6 M H z /1 8 8 k W 4
4 M H z /2 7 5 k W 2
2 .5
2 .7
3 .0 V
3 .5 (V )
4 .0
4 .5
5 .2
5 .5
DD
H T83XXX 10
V v s . F C h a r t (F o r 4 .5 V )
8 F re q u e n c y (M H z )
8 M H z /1 3 9 k W
6 M H z /1 8 4 k W 6
4 M H z /2 7 4 k W 4
2
2 .5
2 .7
3 .0 V
DD
3 .5 (V )
4 .0
4 .5
5 .2
5 .5
Rev. 1.20
8
May 17, 2007
HT83XXX
Functional Description
Execution Flow The system clock for the HT83XXX is derived from either a crystal or RC oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the Program Counter, two cycles are required to complete the instruction. Program Counter - PC The 11-bit program counter (PC) controls the sequence in which the instructions stored in program ROM are executed. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the program counter (PCL) is a read/write register (06H). Moving data into the PCL performs a short jump. The destination must be within 256 locations. When a control transfer takes place, an additional dummy cycle is required.
S y s te m
C lo c k PC
T1
T2
T3
T4
T1
T2
T3
T4
T1
T2
T3
T4
PC
PC+1
PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow
Mode Initial Reset Time Base Overflow Timer Counter 0 Overflow Timer Counter 1 Overflow Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter *10 0 0 0 0 *9 0 0 0 0 *8 0 0 0 0 *7 0 0 0 0 *6 0 0 0 0 *5 0 0 0 0 *4 0 0 0 0 *3 0 0 1 1 *2 0 1 0 1 *1 0 0 0 0 *0 0 0 0 0
Program Counter+2 *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program Counter Note: *10~*0: Program counter bits #10~#0: Instruction code bits S10~S0: Stack register bits @7~@0: PCL bits
Rev. 1.20
9
May 17, 2007
HT83XXX
Program Memory - ROM The program memory stores the program instructions that are to be executed. It also includes data, table and interrupt entries, addressed by the program counter along with the table pointer. The program memory size for HT83XXX is 204815 bits. Certain locations in the program memory are reserved for special usage:
* Location 000H
Table Location Any location in the ROM space can be used as look up tables. The instructions TABRDC [m] (used for any bank) and TABRDL [m] (only used for last page of program ROM) transfer the contents of the lower-order byte to the specified data memory [m], and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined. The higher-order bytes of the table word are transferred to the TBLH. The table higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register, which indicates the table location. Stack Register - Stack The stack register is a special part of the memory used to save the contents of the Program Counter. This stack is organized into four levels. It is neither part of the data nor part of the program space, and cannot be read or written to. Its activated level is indexed by a stack pointer (SP) and cannot be read or written to. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. The program counter is restored to its previous value from the stack at the end of subroutine or interrupt routine, which is signaled by return instruction (RET or RETI). After a chip resets, SP will point to the top of the stack. The interrupt request flag will be recorded but the acknowledgment will be inhibited when the stack is full and a non-masked interrupt takes place. After the stack pointer is decremented (by RET or RETI), the interrupt request will be serviced. This feature prevents stack overflow and allows programmers to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry is lost.
This area is reserved for program initialization. The program always begins execution at location 000H each time the system is reset.
* Location 004H
This area is reserved for the time base interrupt service program. If the ETBI (intc.1) is activated, and the interrupt is enabled and the stack is not full, the program will jump to location 004H and begins execution.
* Location 008H
This area is reserved for the 8-bit Timer Counter 0 interrupt service program. If a timer interrupt results from a Timer Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 008H and begins execution.
* Location 00CH
This area is reserved for the 8-bit Timer Counter 1 interrupt service program. If a timer interrupt results from a Timer Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 00CH and begins execution.
0000H 0004H 0008H 000CH 0015H In itia l A d d r e s s T im e B a s e In te r r u p t S u b r o u tin e T im e r 0 In te r r u p t S u b r o u tin e T im e r 1 In te r r u p t S u b r o u tin e P ro g ra m ROM
07FFH
Program Memory
Instruction TABRDC [m] TABRDL [m]
Table Location *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table Location Note: *10~*0: Current program ROM table P10~P8: Bits of current program counter @7~@0: Write @7~@0 to TBLP pointer register
Rev. 1.20
10
May 17, 2007
HT83XXX
Data Memory - RAM The data memory is designed with 808 bits. The data memory is further divided into two functional groups, namely, special function registers (00H~2AH) and general purpose user data memory (30H~7FH). Although most of them can be read or be written to, some are read only. The general purpose data memory, addressed from 30H~7FH, is used for data and control information under instruction commands. The areas in the RAM can directly handle the arithmetic, logic, increment, decrement and rotate operations. Except some dedicated bits, each bit in the RAM can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through the Memory Pointer register 0 (MP0:01H). Indirect Addressing Register Location 00H is indirect addressing registers that are not physically implemented. Any read/write operation of [00H] accesses the RAM pointed to by MP0 (01H) respectively. Reading location 00H indirectly returns the result 00H. While, writing it indirectly leads to no operation. Accumulator - ACC (05H) The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ etc)
On entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly.
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H
21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH
IA R 0
MP0
ACC PCL TBLP TBLH W DTS STATUS IN T C TM R0 TM R0C TM R1 TM R1C PA PAC PB PBC
LATCH 0H LATCH 0M LATCH 0L
S p e c ia l P u r p o s e D a ta M e m o ry
Status Register - STATUS (0AH) This 8-bit STATUS register (0AH) consists of a zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PDF flags. Operations related to the status register, however, may yield different results from those intended. The TO and PDF flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. Rev. 1.20 11
PW MCR PW ML PW MH V o lu m e C o n tr o l R e g is te r ( V O L ) LATCHD
2FH 30H G e n e ra l P u rp o s e D a ta M e m o ry 7FH
:U nused, re a d a s "0 "
RAM Mapping May 17, 2007
HT83XXX
Address 00H 01H 05H 06H 07H 08H 09H 0AH 0BH 0DH 0EH 10H 11H 12H 13H 14H 15H 18H 19H 1AH 26H 27H 28H 29H 2AH RAM Mapping IAR0 MP0 ACC PCL TBLP TBLH WDTS STATUS INTC TMR0 TMR0C TMR1 TMR1C PA PAC PB PBC LATCH0H LATCH0M LATCH0L PWMCR PWML PWMH VOL LATCHD Read/Write R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Indirect Addressing Register 0 Memory Pointer 0 Accumulator Program counter lower-order byte address Table pointer lower-order byte register Table higher-order byte content register Watchdog Timer option setting register Status register Interrupt control register 0 Timer Counter 0 register Timer Counter 0 control register Timer Counter 1 register Timer Counter 1 control register Port A I/O data register Port A I/O control register Port B I/O data register Port B I/O control register Voice ROM address latch 0 [A17, A16] Voice ROM address latch 0 [A15~A8] Voice ROM address latch 0 [A7~A0] PWM control register
R/W, higher-nibble PWM output data P3~P0 to PWML7~PWML4 available only R/W PWM output data P11~P4 to PWMH7~PWMH0
R/W, higher-nibble Volume control register and volume controlled by VOL8~VOL4 available only R Voice ROM data register
2BH~2FH Unused 30H~7FH User data RAM Note: R: Read only W: Write only R/W: Read/Write Interrupts The HT83XXX provides two 8-bit programmable timer interrupts, and a time base interrupt. The Interrupt Control registers (INTC:0BH) contain the interrupt control bits to set to enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the EMI bit and the corresponding INTC bit may be set to alRev. 1.20 12 low interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then branching to subroutines at the specified location(s) in the program memory. Only the program counter is pushed onto the stack. The programmer must save the contents of the register or status register (STATUS) in advance if they are altered by an interrupt service program which corrupts the desired control sequence. R/W User data RAM
May 17, 2007
HT83XXX
Bit No. 0 Label C Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register The Internal Timer Counter 0 Interrupt is initialized by setting the Timer Counter 0 interrupt request flag (T0F:bit 5 of INTC), caused by a Timer Counter 0 overflow. When the interrupt is enabled, and the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. The Internal Timer Counter 1 Interrupt is initialized by setting the Timer Counter 1 interrupt request flag (T1F:bit 6 of INTC), caused by a Timer Counter 1 overflow. When the interrupt is enabled, and the stack is not full and the T1F bit is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts. Time Base Interrupt is triggered by set INTC.1 (ETBI) which sets the related interrupt request flag (TBF:bit 4 of INTC). When the interrupt is enabled, and the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (TBF) and EMI bits will be cleared to disable other interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgment are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). To return from the interrupt subroutine, the RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit. The Timer Counter 0/1 interrupt request flag (T0F/T1F) which enables Timer Counter 0/1 control bit (ET0I/ ET1I), Rev. 1.20 13 May 17, 2007 the time base interrupt request flag (TBF) which enables time base control bit (ETBI) from the interrupt control register (INTC:0BH) EMI, ETBI, ET0I, ET1I are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt begin serviced. Once the interrupt request flags (T0F, T1F, TBF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. It is recommended that application programs do not use CALL subroutines within an interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt enable is not well controlled, once a CALL subroutine if used in the interrupt subroutine will corrupt the original control sequence. Bit No. Label 0 1 2 3 4 5 6 7 EMI ETBI ET0I ET1I TBF T0F T1F 3/4 Function Controls the master (global) interrupt (1= enabled; 0= disabled) Controls the time base interrupt (1= enabled; 0= disabled) Controls the timer 0 interrupt (1= enabled; 0= disabled) Controls the timer 1 interrupt (1= enabled; 0= disabled) Time base interrupt request flag (1= active; 0= inactive) Timer 0 request flag (1= active; 0= inactive) Timer 1 request flag (1= active; 0= inactive) Unused bit, read as 0 INTC (0BH) Register
1 2 3 4 5 6~7
AC Z OV PDF TO 3/4
HT83XXX
Interrupt Source Time Base Interrupt Timer Counter 0 Overflow Timer Counter 1 Overflow Oscillator Configuration The HT83XXX provides two oscillator circuits for system clock, i.e., RC oscillator and Crystal oscillator. No matter what type of oscillator.. The signal is used for the system clock. The HALT mode stops the system oscillator to conserve power. If the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the range of the resistance should be from 144kW to 275kW. The system clock, divided by 4. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is therefore not suitable for timing sensitive operations where accurate oscillator frequency is desired. On the other hand, if the crystal oscillator is selected, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. A resonator may be connected between OSC1 and OSC2 to replace the crystal and to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required.
OSC1 V
DD
Priority 1 2 3
Vector 04H 08H 0CH
Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided by mask options. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by mask option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. Once the internal WDT oscillator (RC oscillator with period 78ms normally) is selected, it is first divided by 256 (8-stages) to get the nominal time-out period of approximately 20ms. This time-out period may vary with temperature, VDD and process variations. By invoking the WDT prescaler, longer time-out period can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of WDTS(09H)) can give different time-out period. If WS2, WS1, WS0 all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6 seconds. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. The WDT overflow under normal operation will initialize a chip reset and set the status bit TO. Whereas in the HALT mode, the overflow will initialize a warm re set only the Program Counter and SP are reset to zero. To clear the contents of the WDT (including the WDT prescaler), three methods are adopted; external reset (external reset (a low level to RES), software instructions, or a HALT instruction. The software instruction is CLR WDT and execution of the CLR WDT instruction will clear the WDT.
OSC1
OSC2 C r y s ta l O s c illa to r
fS
YS
/4
RC
OSC2
O s c illa to r
System Oscillator
WS7 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
WS6 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
WS5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
WS4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
WS3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
WS2 0 0 0 0 1 1 1 1
WS1 0 0 1 1 0 0 1 1
WS0 0 1 0 1 0 1 0 1
Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
WDTS (09H) Register
Rev. 1.20
14
May 17, 2007
HT83XXX
S y s te m C lo c k /4 M ask O p tio n S e le c t W D T P r e s c a le r 8 - b it C o u n te r 7 - b it C o u n te r
W DT OSC
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer Power Down - HALT The HALT mode is initialized by a HALT instruction and results in the following:
* The system oscillator will be turned off but the WDT
abled. To minimize power consumption, all I/O pins should be carefully managed before entering the HALT status. Reset There are 3 ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
oscillator keeps running (if the WDT oscillator is selected).
* The contents of the on chip RAM and registers remain
unchanged.
* WDT and WDT prescaler will be cleared and recount
again.
* All I/O ports maintain their original status. * The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. By examining the TO and PDF flags, the reason for the chip reset can be determined. The PDF flag is cleared when the system powers-up or executes the CLR WDT instruction, and is set when the HALT instruction is executed. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer. The other maintain their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If awakening from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled by the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. Once a wake-up event occurs, it takes 1024 system clock period to resume normal operation. In other words, a dummy cycle period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge, the actual interrupt subroutine will be delayed by one more cycle. If the wake-up results in next instruction execution, this will be executed immediately after a dummy period is finished. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be dis-
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that resets only the Program Counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during any other reset conditions. Most registers are reset to their initial condition when the reset conditions are met. By examining the PDF flag and TO flag, the program can distinguish between different chip resets. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
Note: u stands for unchanged
V
DD
RES
Reset Circuit
VDD RES S S T T im e - o u t C h ip R eset tS
ST
Reset Timing Chart 15 May 17, 2007
Rev. 1.20
HT83XXX
To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses after a system power up or when awakening from a HALT state. When a system power up occurs, the SST delay is added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any wake-up from HALT will enable the SST delay.
HALT W DT W DT T im e - o u t R eset W a rm R eset
The functional unit chip reset status are shown below. Program Counter Interrupt Prescaler WDT Timer Counter Input/Output Ports Stack Pointer 000H Disable Clear Clear. After master reset, WDT begins counting Off Input mode Points to the top of the stack
RES SST 1 0 -s ta g e R ip p le C o u n te r P o w e r - o n D e te c tin g C o ld R eset
OSCI
Reset Configuration Timer Counter 0/1 The TMR0/TMR1 is internal clock source only, i.e. (TM1, TM0) = (0, 1). There is a 3-bit prescaler (TMRS2, TMRS1, TMRS0) which defines different division ratio of TMR0/TMR1s clock source. Bit No. Label Function Defines the operating clock source (TMRS2, TMRS1, TMRS0) 000: clock source/2 001: clock source/4 010: clock source/8 011: clock source/16 100: clock source/32 101: clock source/64 110: clock source/128 111: clock source/256 Defines the TMR0/TMR1 active edge of Timer Counter Enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read as 0 Defines the operating mode (TM1, TM0) TMR0C (0EH)/TMR1C (11H) Register Note: TMR0C/TMR1C bit 3 always write 0 TMR0C/TMR1C bit 5 always write 0 TMR0C/TMR1C bit 6 always write 1 TMR0C/TMR1C bit 7 always write 0
(T M R S 2 , T M R S 1 , T M R S 0 ) S y s te m C lo c k 8 -S ta g e P r e s c a le r TON O v e r flo w to In te rru p t T im e r C o u n te r 0 /1 P r e lo a d R e g is te r
0~2
TMRS2, TMRS1, TMRS0
3 4 5 6 7
TE TON 3/4 TM0, TM1
D a ta B u s R e lo a d
T im e r C o u n te r 0 /1
Timer Counter 0/1 Rev. 1.20 16 May 17, 2007
HT83XXX
The TMR0C is the Timer Counter 0 control register, which defines the Timer Counter 0 options. The Timer Counter 1 has the same options as the Timer Counter 0 and is defined by TMR1C. To enable the counting operation, the Timer ON bit (TON; bit 4 of TMR0C/TMR1C) should be set to 1. The overflow of the timer counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I/ET1I can disable the corresponding interrupt service. The TMR0/1 is internal clock source only. There is a 3-bit prescaler (TMRS2, TMRS1, TMRS0) which defines different division ratio of TMR0/1s clock source. Time Base The time base enables the counting operation by INTC.1 (ETBI) bit. The overflow to interrupt as set INTC.4. The time base is internal clock source only. Time base of 1ms to overflow as system clock is 4MHz. Time base of 0.5ms to overflow as system clock is 8MHz.
S y s te m C lo c k /4
1024
O v e r flo w to In te rru p t
Time Base
The registers states are summarized in the following table. Register Reset (Power-on) MP0 ACC Program Counter xxxx xxxx xxxx xxxx 0000H xxxx xxxx TBLH WDTS STATUS INTC TMR0 TMR0C TMR1 TMR1C PA PAC PB PBC LATCH0H LATCH0M LATCH0L PWMCR PWML PWMH VOL LATCHD Note: xxxx xxxx 0000 0111 --00 xxxx -000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1111 1111 1111 1111 ---- 1111 ---- 1111 ---- --xx xxxx xxxx xxxx xxxx 0--- 00-0 xxxx ---xxxx xxxx xxxx ---xxxx xxxx WDT Time-out RES Reset (Normal Operation) (Normal Operation) uuuu uuuu uuuu uuuu 0000H uuuu uuuu uuuu uuuu 0000 0111 --1u uuuu -000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1111 1111 1111 1111 ---- 1111 ---- 1111 ---- --uu uuuu uuuu uuuu uuuu u--- uu-u uuuu ---uuuu uuuu uuuu ---uuuu uuuu uuuu uuuu uuuu uuuu 0000H uuuu uuuu uuuu uuuu 0000 0111 --uu uuuu -000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1111 1111 1111 1111 ---- 1111 ---- 1111 ---- --uu uuuu uuuu uuuu uuuu u--- uu-u uuuu ---uuuu uuuu uuuu ---uuuu uuuu RES Reset (HALT) uuuu uuuu uuuu uuuu 0000H uuuu uuuu uuuu uuuu 0000 0111 --01 uuuu -000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1111 1111 1111 1111 ---- 1111 ---- 1111 ---- --uu uuuu uuuu uuuu uuuu u--- uu-u uuuu ---uuuu uuuu ---uuuu uuuu WDT Time-out (HALT) uuuu uuuu uuuu uuuu 0000H uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu ---- uuuu ---- uuuu ---- --uu uuuu uuuu uuuu uuuu u--- uu-u uuuu ---uuuu uuuu uuuu ---uuuu uuuu
u means unchanged x means unknown - means undefined
Rev. 1.20
17
May 17, 2007
HT83XXX
Input/Output Ports There are 12 bidirectional input/output lines in the microcontroller, labeled from PA to PB, which are mapped to the data memory of [12H], [14H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A, [m] (m=12H, 14H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13Hm 15H. After a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. The wake-up capability of port A is determined by mask option. There is a pull-high option available for all I/O lines. Once the pull-high option is selected, all I/O lines have pull-high resistors. Otherwise, the pull-high resistors are absent. It should be noted that a non-pull-high I/O line operating in input mode will cause a floating state.
D a ta B u s D W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D W r ite I/O
Q CK S
V
DD
Q
V
DD
W eak P u ll- u p M a s k O p tio n PA0~PA7 PB0~PB3
Q CK S
Q
M
R e a d I/O S y s te m W a k e - U p ( P A o n ly ) M a s k O p tio n
U X
Input/Output Ports
Rev. 1.20
18
May 17, 2007
HT83XXX
Pulse Width Modulation Output - PWML/PWMH (27H/28H) The HT83XXX provide one 12-bit PWM interface for driving an external 8W speaker. The programmer must write the voice data to register PWML/PWMH (27H/28H) Pulse Width Modulation Control Register - PWMCR (26H) Bit 7 MSB_SIGN Bit 6 3/4 Bit 5 3/4 Bit 4 3/4 Bit 3 (R/W) Single_PWM Bit 2 (R/W) VROMC Bit 1 3/4 Bit 0 (R/W) PWMC
PWMC: Start bit of PWM output
* PWM start counter: 0 to 1 * PWM stop counter: 1 to 0
Voice ROM Data Address Latch Counter The voice ROM data address latch counter is the handshaking between the microcontroller and voice ROM, where the voice codes are stored. One 8-bit of voice ROM data will be addressed by setting 18-bit address latch counter LATCH0H/LATCH0M/LATCH0L. After the 8-bit voice ROM data is addressed, a few instruction cycles (4ms at least) will be generated to latch the voice ROM data, then the microcontroller can read the voice data from LATCHD (2AH). Example: Read an 8-bit voice ROM data which is located at address 000007H by address latch 0 set mov mov mov mov mov mov call mov [26H].2 A, 07H A, 00H A, 00H Delay Time A, LATCHD ; Enable voice ROM circuit ; ; ; ; Delay a short period of time ; Get voice data at 000007H
After waiting one cycle end , stop the PWM counter and keep in low signal VROMC: Enable voice ROM power circuit (1=enable; 0=disable) Single_PWM: Driving PWM signal by PWM1 output. (1=PWM1 output; 0=PWM1/PWM2 output) The HT83XXX provide an 12-bit (bit 7 is a sign bit, if Single_PWM = 0) PWM interface. The PWM provides two pad outputs: PWM1, PWM2 which can directly drive a piezo or an 8W speaker without adding any external element (green mode), or using only port PWM1 (Set Single_PWM = 1) to drive piezo or an 8W speaker with external element. When Setting Single_PWM= 1, choose voice data7~ data1 as the output data (no sign bit on it). If the sign bit is 0, then the signal is output to PWM1and the PWM2 will get a GND level voltage after setting start bit to 1. If the sign bit is 1, then the signal is output to PWM2 and the PWM1 will get a GND level voltage after setting start bit to 1. PWM output Initial low level , and stop in low level If PWMC from low to high then start PWM output latch new data , if no update then keep the old value. If PWMC from high to low, in duty end, stop PWM output and stop the counter.
LATCH0L, A ; Set LATCH0L to 07H LATCH0M, A ; Set LATCH0M to 00H LATCH0H, A ; Set LATCH0H to 00H
D a ta B u s P W M D a ta B u ffe r (2 8 H ) F1 B it7 ( s ig n b it) V
DD
S y s te m
C lo c k
P r e s c a le r F0
S ta r t b it 2 6 H .0 PW MI F2
D iv .
CK PE
7 B its C o u n te r ( B it6 ~ B it0 ) O v e r flo w D
Q CK Q
R
P W M 1 fo r S p e a k e r
P W M 2 fo r S p e a k e r
PWM Rev. 1.20 19 May 17, 2007
HT83XXX
Mask Option Mask Option PA Wake-up Watchdog Timer (WDT) PA Pull-high PB Pull-high OSC Option fOSC - RTYPICAL Table (VDD=3V) fOSC 4MHz10% 6MHz10% 8MHz10% RTYPICAL 275kW 188kW 144kW Description Enable or disable PA wake-up function Enable or disable WDT function WDT clock source is from WDTOSC or T1 Enable or disable PA pull-high Enable or disable PB pull-high Crystal or Resistor type
Application Circuits
V
DD
VDD VSS OSC1 R V
DD OSC
V VDDP 100kW
DD
47mF RES VSSP
0 .1 m F C
PA0~PA7 PB0~PB3 H T83XXX
PW M1 PW M2
S peaker (8 W /1 6 W )
Single PWM Mode
V
DD
VDD VSS
OSC2 4M H z~8M H z OSC1 V VDDP
DD
V
DD
100kW 0 .1 m F C RES VSSP
47mF
V
DD
S peaker (8 W /1 6 W ) Q2 NPN BCE
PA0~PA7 PB0~PB3 H T83XXX
PW M1
Rev. 1.20
20
May 17, 2007
HT83XXX
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
Rev. 1.20
21
May 17, 2007
HT83XXX
Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
Rev. 1.20
22
May 17, 2007
HT83XXX
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
Rev. 1.20
23
May 17, 2007
HT83XXX
AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr
Operation Affected flag(s)
TO 3/4 CLR [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.20
24
May 17, 2007
HT83XXX
CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation Affected flag(s) TO 0 CLR WDT1 Description PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CLR WDT2 Description
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CPL [m] Description Operation Affected flag(s) TO 3/4
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m]
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Rev. 1.20
25
May 17, 2007
HT83XXX
CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m]
Operation Affected flag(s)
TO 3/4 DAA [m] Description
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s) TO 3/4 DEC [m] Description Operation Affected flag(s) TO 3/4 DECA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
Rev. 1.20
26
May 17, 2007
HT83XXX
HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0
Operation
Affected flag(s) TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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HT83XXX
MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
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HT83XXX
RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation Affected flag(s) TO 3/4 RETI Description Operation Affected flag(s) TO 3/4 RL [m] Description Operation Affected flag(s) TO 3/4 RLA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7
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HT83XXX
RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7
Affected flag(s) TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7
Operation
Affected flag(s) TO 3/4 RR [m] Description Operation Affected flag(s) TO 3/4 RRA [m] Description Operation Affected flag(s) TO 3/4 RRC [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0
Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rev. 1.20
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May 17, 2007
HT83XXX
RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0
Operation
Affected flag(s) TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1)
Operation Affected flag(s)
TO 3/4 SDZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1)
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.20
31
May 17, 2007
HT83XXX
SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1)
Operation Affected flag(s)
TO 3/4 SIZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1)
Operation Affected flag(s)
TO 3/4 SNZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.20
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HT83XXX
SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
Rev. 1.20
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May 17, 2007
HT83XXX
SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation Affected flag(s) TO 3/4 TABRDL [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.20
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May 17, 2007
HT83XXX
XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
Rev. 1.20
35
May 17, 2007
HT83XXX
Package Information
28-pin SOP (300mil) Outline Dimensions
28 A
15 B
1
14
C C' G H D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 697 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 713 104 3/4 3/4 38 12 10
Rev. 1.20
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HT83XXX
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301 621.5 13+0.5 -0.2 20.5 24.8+0.3 -0.2 30.20.2
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May 17, 2007
HT83XXX
Carrier Tape Dimensions
D
E F
P0
P1
t
W C
B0
D1
P
K0 A0
SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 240.3 120.1 1.750.1 11.50.1 1.5+0.1 1.5+0.25 40.1 20.1 10.850.1 18.340.1 2.970.1 0.350.01 21.3
Rev. 1.20
38
May 17, 2007
HT83XXX
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
39
May 17, 2007

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